Dynamic random-access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor of a DRAM storage cell within an integrated circuit. Embedded DRAM (eDRAM) is a DRAM integrated with logic circuits on the same die or chip of a semiconductor integrated circuit. Integrated circuits with eDRAIVI have a higher content of logic circuit elements (e.g., FinFETs, transistors, diodes or the like) in close proximity to the eDRAM cells, and more specifically to the eDRAIVI capacitors, than that of conventional integrated circuits with high density DRAM.
One of the largest applications for DRAM (and eDRAM) cells is in the main memory in modern computers, wherein multiple DRAM cells are disposed in memory modules of the computers. One of the advantages of DRAM is its structural simplicity. That is, only one transistor and one capacitor are required per DRAM cell in order to store a bit of data.
Generally, DRAM cell capacitors are fabricated in the middle-end-of-line (MEOL) portion of a conventional semiconductor fabrication process. Problematically however, DRAM cell capacitors are typically subjected to high enough process temperatures (e.g., 600-700 degrees centigrade) to cause significant performance deviations in conventional logic devices such as FinFETs, diodes and similar, which are fabricated in the front-end-of-line (FEOL). As such, many standard logic circuits and standard logic fabrication processes cannot be used with conventional DRAM process steps added into the MEOL.
In contrast, in a conventional prior art eDRAIVI cell, for example, in a FinFET or planar CMOS semiconductor structure, the capacitor is formed in the back-end-of-line (BEOL) and the transistor is formed in the front-end-of-line (FEOL). Accordingly, logic circuits formed in the FEOL are much less affected by the capacitor process temperatures in the BEOL for prior art eDRAM. As such, circuits with conventional eDRAM processed in the BEOL are generally more logic compatible than circuits with conventional DRAM processed in the MEOL.
Problematically however, the capacitor and its associated transistor of the conventional eDRAIVI cell are typically separated by several layers of semiconductor materials through which multiple vias must be formed in order to make the proper electrical connections to form a functional cell. Furthermore, the dielectric used in the formation of eDRAM cell capacitors (typically Si-nitride) generally has poorer quality with higher leakage than other semiconductor capacitors, thus leading to a need for a relatively thicker dielectric for the eDRAM cell capacitor. This tends to increase the overall footprint of the eDRAM cells and to increase the process complexity required to manufacture the eDRAM cells.
Accordingly, there is a need for an eDRAM cell structure, and method of making the same, wherein both the capacitor and transistor are formed in the FEOL. Additionally, there is a need to decrease the footprint of the eDRAIVI cell and to simplify the process flow required to form the eDRAM cell. Additionally, there is a need to form the capacitor of an eDRAM cell with a lower temperature process than conventional DRAM cell fabrication at the MEOL.